High speed serial link communications are an important function of many integrated circuits and systems. However, implementing high speed serial link communications also provides many challenges. For example, a 56 gigabyte per second (Gb/s) serializer/deserialzer (SerDes) circuit implemented in a data transmission channel having high loss requires sophisticated equalization to achieve a targeted error rate. In conventional devices, the equalization is done with a FFE (Feed Forward Equalizer) to cancel out pre-cursor inter-symbol interference (ISI) and a Decision Feedback Equalizer (DFE) to cancel out residual post-cursor ISI. However, conventional circuits implementing the FFE and DFE equalization can only support a few DFE taps, due to limitations in implementing the DFE in an integrated circuit. Because of the feedback loop in DFE, loop unrolling is necessary to achieve a high data rate. Further, as the number of DFE taps increases, the critical path length increases, and the complexity of the loop unrolling of the DFE also increases exponentially. To support even higher data rates and more challenging transmission channels, improved circuits implementing FFE and DFE equalization is necessary.
Accordingly, improved circuits and methods for filtering inter-symbol interference in an integrated circuit would be advantageous.